1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to the structure where electrical connection is carried out between an upper interconnection layer and a lower interconnection layer which is a portion of a cell plate, and a method of manufacturing that structure.
2. Description of the Background Art
The demand of semiconductor memory devices is rapidly growing in accordance with the significant spread of information equipment such as computers. Semiconductor memory devices having a large functional storage capacity and that can operate at high speed are required. In response, technical development of semiconductor memory devices regarding increase in integration density and high speed response is carried out.
One type of a semiconductor memory device is a DRAM (Dynamic Random Access Memory) capable of random input/output of information data. A DRAM generally includes a memory cell array which is the storage region for storing a plurality of information signals, and a peripheral circuit required for carrying out input/output with an external source.
FIG. 34 is a block diagram showing a structure of a conventional DRAM. Referring to FIG. 34, a DRAM 1000 includes a memory cell array 1100 for storing a data signal of information, a row and column address buffer 1200 for receiving an externally applied address signal to select a memory cell forming a unit storage circuit, a row decoder 8300 and a column decoder 1400 for specifying a memory cell by decoding an address signal, a sense refresh amplifier 1500 for amplifying and reading out a signal stored in a specified memory cell, a data-in buffer 1600 and a data-out buffer 1700 for data input/output, and a clock generator 1800 for generating a clock signal.
Memory cell array 1100 occupying a large area on a semiconductor chip has a plurality of memory cells arranged in a matrix for storing unit storage information. FIG. 35 is an equivalent circuit diagram of memory cells of 4 bits forming memory cell array 1100. The illustrated memory cell is a so-called one transistor-one capacitor type memory cell formed of one MOS (Metal Oxide Semiconductor) transistor 1900 and one capacitor 2000 connected thereto. This type of memory cell is widely used in a DRAM of large capacity because it facilitates increase of the integration density of a memory cell array due to its simple structure.
A DRAM memory cell can be divided into several types according to the structure of its capacitor. FIG. 36 is a sectional view of a memory cell having a typical stacked-type capacitor, and is shown in Japanese Patent Publication No. 60-2784, for example. Referring to FIG. 36, the memory cell includes one transfer gate transistor and one stacked type capacitor (referred to as "stacked type capacitor" hereinafter).
A transfer gate transistor includes source/drain regions 5a and 5b formed at the main surface of a silicon substrate 1, and a gate electrode (word line) 7 formed on the main surface of silicon substrate 1 between source/drain region 5a and source/drain region 5b. A stacked type capacitor includes a storage node 9 electrically connected to source/drain region 5b and extending upon field oxide film 3, a dielectric film 11 formed at the surface of storage node 9, and a cell plate 13 formed at the surface of dielectric film 11.
An interlayer insulating film 17 is formed to cover the transfer gate transistor and the stacked type capacitor. A bit line 15 is formed on interlayer insulating film 17. A through hole is formed in interlayer insulating film 17. Bit line 15 is electrically connected to source/drain region 5a via this through hole.
A feature of this stacked type capacitor is that the capacitance of a capacitor is ensured by extending the main portion of the capacitor upon the gate electrode and the field oxide film to increase the opposing area between electrodes in the capacitor.
The capacity of a capacitor is generally proportional to the opposing area of electrodes and is inversely proportional to the thickness of the dielectric film. It is preferable to increase the opposing area between electrodes of a capacitor from the standpoint of increasing the capacity of a capacitor. However, the size of a memory cell is significantly reduced in accordance with increase in the integration density of a DRAM. This means that the capacitor formation region has its planar occupying area reduced. The amount of charge stored in a memory cell of 1 bit can not be reduced from the standpoint of stable operation and reliability of a DRAM as a memory device. In order to satisfy these contradicting constraints, various improvements have been proposed for the structure of the capacitor to reduce the planar occupying area of the capacitor and to increase the opposing area between electrodes.
FIG. 37 is a sectional view of a memory cell disclosed in Japanese Patent Laying-Open No. 4-755. A storage node 23 of the capacitor of this memory cell includes a base portion 23a, and a wall portion 23b extending upwards with respect to the main surface of a silicon substrate 21. The capacity of the capacitor can be increased by this wall portion 23b without increasing the planar occupying area of the capacitor.
The structure of this memory cell will be described specifically. On the main surface of silicon substrate 21, source/drain regions 25a, 25b, and 25c are formed spaced apart. Base portion 23a is electrically connected to source/drain region 25c. A dielectric film 27 is formed at the surface of storage node 23. A cell plate 29 is formed at the surface of dielectric film 27.
Gate electrodes 31a and 31b spaced apart are formed above the main surface of silicon substrate 21. Gate electrodes 31a and 31b are covered with an insulating film 33. 35 indicates a field oxide film.
An interlayer insulating film 37 is formed on cell plate 29. Interconnection films 39 are formed spaced apart on interlayer insulating film 37. Interconnection films 39 are covered with a protection film 41. A method of manufacturing this memory cell will be described hereinafter.
Referring to FIG. 38, a field oxide film 35 is formed at the main surface of silicon substrate 21 using a LOCOS method.
Referring to FIG. 39, a gate oxide film 43 is formed by thermal oxidation. Then, gate electrodes 31a, 31b, 31c, 31d of polycrystalline silicon are selectively formed. An insulating film 33 is formed around gate electrodes 31a-31d by two steps of a deposition step of an oxide film and an etching step. Using insulating film 33 as a mask, impurities are implanted to the main surface of silicon substrate 21 by ion implantation to form source/drain regions 25a, 25b, and 25c.
Referring to FIG. 40, a refractory metal film is deposited and patterned to a predetermined configuration. Thus, a bit line 45 electrically connected to source/drain region 25b is formed. An insulating film 47 covers the circumference of bit line 45.
Referring to FIG. 41, a polycrystalline silicon film 49 is formed all over the main surface of silicon substrate 21 by CVD method.
Referring to FIG. 42, an insulating film 51 is formed on polycrystalline silicon film 49.
Referring to FIG. 43, a resist 53 is applied on the surface of insulating film 51 to be subjected to a lithography method to result in a predetermined pattern.
Referring to FIG. 44, insulating film 51 is selectively removed by etching using resist 53 as a mask.
Referring to FIG. 45, a polycrystalline silicon film 55 is formed by CVD after removal of resist 53.
Referring to FIG. 46, a thick resist 57 is applied so that polycrystalline silicon film 55 is completely covered. Then, resist 57 is etched back to expose polycrystalline silicon film 55 covering the upper surface of insulating film 51.
Referring to FIG. 47, the exposed polycrystalline silicon film 55 is etched. Then, insulating layer 51 is removed by etching in a self-alignment manner. Thus, polycrystalline silicon film 55 becomes the wall portion 23b.
Referring to FIG. 48, only the exposed portion of polycrystalline silicon film 49 is removed in a self-alignment manner by anisotropic etching. Thus, polycrystalline silicon film 49 becomes the base portion 23a. Then, resist 57 is removed.
Referring to FIG. 49, a dielectric film 27 of silicon nitride film is formed on the surface of storage node 23.
Referring to FIG. 50, a cell plate 29 of a polycrystalline silicon film is formed all over the main surface of silicon substrate 21.
Referring to FIG. 51, an interlayer insulating film 37 is formed on cell plate 29. An interconnection film 39 of aluminum is formed on interlayer insulating film 37, as shown in FIG. 37, to cover protection film 41. Thus, the manufacture process of a memory cell is completed.
Under the condition shown in FIG. 51, the area other than the memory cell formation region is as shown in FIG. 52. The memory cell formation region is indicated by A. In order to provide electrical connection between cell plate 29 and the upper layer interconnection film, a portion of cell plate 29 extends upon interlayer insulating film 65. This portion of cell plate 29 is referred to as the lower layer interconnection film 30. Gate electrodes 31e and 31f are formed in the memory cell formation region. The MOS transistor is indicated by 63. MOS transistor 63 includes source/drain regions 61a and 61b. Dielectric film 27 of the capacitor is formed all over silicon substrate 21 as shown in FIG. 52. The impurity region is indicated by 59. The method of providing electrical connection between lower layer interconnection film 30 and the upper layer interconnection film will be described hereinafter.
Referring to FIG. 53, a resist 69 is applied on interlayer insulating film 37. A predetermined patterning is applied to resist 69. Interlayer insulating films 37 and 65 are selectively removed by anisotropic etching using resist 69 as a mask to form through holes 67a, 67b, 67c, and 67d.
Referring to FIG. 54, resist 69 is removed. Using a CVD method, a tungsten film 71 is formed on interlayer insulating film 37. The CVD method is used because a through hole can not be completely filled by sputtering if the aspect ratio of the through hole (depth of the hole/opening dimension of the hole) is increased. Tungsten film 71 is formed also inside the through hole to provide electrical connection with lower layer interconnection film 30, impurity region 59, and source/drain regions 61a and 61b.
Tungsten film 71 is etched all over using pseudo anisotropic etching where the ratio of anisotropy to isotropy is 2:1. Then, tungsten film 71 is removed leaving tungsten within through holes 67a, 67b, 67c, and 67d. Pseudo anisotropic etching is used to ensure that no tungsten remains at the stepped portion (not shown) of interlayer insulating film 37. Because the thickness of tungsten film 71 can not be formed in uniform and the etching rate differs depending upon the position on the semiconductor device arranged on the wafer, there are cases where tungsten film 71a still remains in other areas even when tungsten film 71 on interlayer insulating film 37 is removed as shown in FIG. 55.
Tungsten film 71 is further etched to remove tungsten film 71a remaining on interlayer insulating film 37. This will cause a portion of tungsten film 71 in through hole 67b to be etched away. In through hole 67a which is shallow in depth, tungsten film 71 will be completely etched away with a portion of the lower interconnection film 30 also etched. FIG. 57 shows the state where an aluminum film is formed on interlayer insulating film 37 by sputtering which is subjected to a predetermined patterning. It is appreciated from FIG. 57 that the electrical connection between lower layer interconnection film 30 and interconnection film 39 formed in through hole 67a is defective.